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HD74LS166A
8-bit Shift Register
REJ03D0450-0400 Rev.4.00 May 10, 2006 The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift register has a complexity of 77 equivalent gates on a monolithic chip. This device features gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse, during parallel loading, serial data flow is inhibited. This, of course, allows the system clock to be free running and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Features
* Ordering Information
Part Name HD74LS166AP Package Type DILP-16 pin Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P Taping Abbreviation (Quantity) --
Pin Arrangement
Serial Input A Parallel Inputs B C D Clock Inhibit Clock GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC Shift/ Load Parallel Input H Output QH G F E Clear Parallel Inputs
(Top view)
Rev.4.00, May 10, 2006, page 1 of 7
HD74LS166A
Function Table
Inputs Clear L H H H H H Shift Load X X L H H X Clock Inhibit X L L L L H Clock X L Serial X X X H L X Parallel A...H X X a...h X X X Internal outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0
Notes: 1. H; high level, L; low level, X; irrelevant 2. ; transition from low to high level 3. a to h; the level of steady-state input at inputs A to H respectively 4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established. 5. QAn to QGn; the level of QA to QG, respectively, before the most recent transition of the clock.
Rev.4.00, May 10, 2006, page 2 of 7
HD74LS166A
Block Diagram
Clear Serial Input Shift/Load A R CK S QA B R CK S QB C R CK S QC D R CK S QD E R CK S QE F R CK S QF G R CK S QG H Clock Clock Inhibit QH R CK S
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.4.00, May 10, 2006, page 3 of 7
HD74LS166A
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock and clear pulse width Mode control setup time Data setup time Hold time Symbol VCC IOH IOL Topr clock tw tsu tsu th Min 4.75 -- -- -20 0 20 30 20 0 Typ 5.00 -- -- 25 -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- Unit V A mA C MHz ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** Input clamp voltage IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 20 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 32 -1.5 Unit V V V V A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
Notes: * VCC = 5 V, Ta = 25C ** With the outputs open, 4.5 V applied to the serial input and all other inputs except the clock grounded, ICC is measured after a momentary ground, then 4.5 V, is applied to clock.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Symbol max tPHL tPHL tPLH Inputs Clear Clock min. 25 -- 7 5 typ. 35 19 14 11 max. -- 30 25 20 Unit MHz ns ns ns Condition
CL = 15 pF, RL = 2 k
Rev.4.00, May 10, 2006, page 4 of 7
HD74LS166A
Testing Method
Test Circuit
4.5V VCC
Input P.G. Zout = 50
Clear Serial Input Shift/Load A QH B C D E F G H Clock Clock Inhibit
RL Output
See Testing Table
CL
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Testing table
Data inputs Data H Serial-in Shift / Load 0V 4.5 V Output QH QH Bit time tn + 1 tn + 8
Rev.4.00, May 10, 2006, page 5 of 7
HD74LS166A Waveform
tw (Clear) 3V Clear Input 1.3V 1.3V 0V tn Clock Input tn + 1 tn tn + 1 3V 1.3V tw (Clock) Data Input tPHL Output QH 1.3V 1.3V tsu 1.3V th 1.3V tPLH 1.3V tPHL VOH 1.3V 1.3V 1.3V VOL tsu 1.3V 0V th 3V 1.3V 0V
Notes:
1. Input pulse; 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50% Clock input; tw 20 ns Clear inpu; tw 20 ns, th = 10 ns, when testing max, vary the clock PRR. 2. Propagation delay time (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified at tn + 8 with a functional test. 3. tn; bit time before clocking transition. tn + 1; bit time after one clocking transition. tn + 8; bit time after eight clocking transition.
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
Clock Clock Inhibit Clear Serial Input Shift / Load A B C Parallel Inputs D E F G H Output QH
H L H L H L H H H H L H L H L H L
Clear
Serial Shift
Load Inhibit
Serial Shift
Rev.4.00, May 10, 2006, page 6 of 7
HD74LS166A
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
Rev.4.00, May 10, 2006, page 7 of 7
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